SR latch and D latch: truth tables, NOR vs NAND latches, and the invalid state

By Muaz Notiar, founder of Tangibool Published 7 November 2026 9 min read

A latch is the simplest memory circuit: two gates that feed each other hold one bit. An SR latch is set by S and reset by R, and must not get both at once; a D latch copies its input D while its enable is on and holds it when the enable is off.

This guide gives the truth tables of the NOR latch (active-high inputs) and the NAND latch (active-low inputs), shows what goes wrong with the invalid input, builds the gated SR latch and the D latch, and derives each one's next-state equation from its gates. The truth tables are computed by the Tangibool engine, which treats the stored value Q as one more input; the tools check the logic and do not simulate delays.

How two gates remember

A logic gate on its own has no memory: its output depends only on its present inputs. Connect two gates in a loop, each one's output feeding the other's input, and the pair can sit in either of two stable states. That is a latch.

The NOR latch has two NOR gates. The output Q comes from one gate and the opposite output Q′ from the other:

Q = NOR(R, Q′) and Q′ = NOR(S, Q)

With both inputs at 0, a NOR gate acts as an inverter on its other input, so the two gates form a loop of two inverters, which is stable with Q = 1, Q′ = 0 or with Q = 0, Q′ = 1. The latch holds whichever it was last put in: substituting S = R = 0 gives NOR(0, NOR(0, Q)) = Q.

The SR latch with NOR gates

Truth table

Q is the stored value and Q+ the value after the inputs have taken effect. The inputs are active-high: a 1 on S sets the latch, a 1 on R resets it.

The next-state equation, from the gates

Substitute the second gate into the first: Q+ = NOR(R, NOR(S, Q)) = R′·(S + Q). The equivalence checker confirms the algebra. With Q as an input, the engine computes the whole table, including the invalid rows:

Computed by the Tangibool engine

On rows 0 to 5 the two outputs are opposites, as they should be. On rows 6 and 7, where S = R = 1, both are 0: the truth table generator shows that “S and R imply both outputs are 0” is true on every row.

On the allowed rows the gate equation R′·(S + Q) equals the textbook characteristic equation Q+ = S + R′·Q: “not both S and R” implies they agree. The two differ only on S = R = 1, where the NOR latch resets, and the textbook equation, which treats that row as a don't-care, says set.

Why S = R = 1 is invalid

Two things go wrong. First, the outputs Q and Q′ are both 0, so Q′ is no longer the opposite of Q, and any circuit that relies on that breaks. Second, when S and R both return to 0 at the same moment, each gate starts to turn the other's output back on, and the latch settles into whichever state the faster gate wins, or oscillates for a while first. The result is unpredictable, so designs never apply S = R = 1, or use a circuit, such as the D latch below, that cannot.

The SR latch with NAND gates

Two NAND gates make the same circuit with active-low inputs, written S̄ and R̄ (S bar and R bar): a 0 sets or resets the latch, and 1 on both holds.

Q = NAND(S̄, Q′) and Q′ = NAND(R̄, Q)

Substituting the gates gives Q+ = NAND(S̄, NAND(R̄, Q)) = S̄′ + R̄·Q, which the equivalence checker confirms. Since S = S̄′ and R = R̄′, that is S + R′·Q: the NAND latch computes the textbook equation exactly, and with both inputs active it sets. Its invalid state is the mirror image of the NOR latch's: both outputs are 1.

In the engine's notation the active-low inputs are written S_bar and R_bar:

Computed by the Tangibool engine

Rows 0 and 1, with S̄ = R̄ = 0, are the invalid ones, with both outputs T.

NOR latch vs NAND latch

A classic use of the NAND latch is debouncing a switch. A mechanical switch bounces for a few milliseconds when it moves, and its contact opens and closes many times. Wire the two positions of a changeover switch to S̄ and R̄: the first touch sets or resets the latch, and the bounces only repeat the same input, so the output changes once.

The gated SR latch

A gated SR latch adds an enable input E, sometimes called the clock or control input. Two more gates pass S and R to the latch only while E = 1; while E = 0, the latch holds whatever the inputs do.

Built from four NAND gates, NAND(S, E) and NAND(R, E) feed a NAND latch, and the next state is NAND(NAND(S, E), NAND(NAND(R, E), Q)). The equivalence checker shows it equals E′·Q + E·(S + R′·Q): hold when E = 0, and behave like an SR latch when E = 1.

The D latch

The D latch removes the invalid input altogether. It is a gated SR latch whose S and R come from one data input, D: S = D and R = D′. S and R can then never both be 1: the latch inputs D·E and D′·E can never both be 1.

While E = 1 the output follows D, so the latch is said to be transparent; when E falls to 0, it keeps the last value of D. With Q as an input:

Computed by the Tangibool engine

The 1s are rows 1 and 3 (enable off, Q = 1) and rows 6 and 7 (enable on, D = 1). The Karnaugh map solver groups them as E·D and E′·Q, so

Q+ = E·D + E′·Q

That is a 2-to-1 multiplexer that chooses D when E = 1 and its own output when E = 0. The four-NAND version, with D′ made by an inverter, computes the same.

One detail from circuit design: when E falls while D and Q are both 1, the E·D term can turn off a moment before the E′·Q term turns on, and the output can glitch. Adding the redundant term D·Q, the consensus of the other two, prevents it, and the equivalence checker confirms the extra term does not change the function. Tangibool's tools show that the term is redundant; the glitch itself is timing, which they do not model.

Latch vs flip-flop

A latch is level-sensitive: while its enable is active, its output follows its inputs. A flip-flop is edge-triggered: it samples its inputs only at the moment the clock changes, a rising or falling edge, and ignores them the rest of the time. A common edge-triggered D flip-flop is two D latches in series, enabled on opposite halves of the clock, so the output can change only once per clock cycle. That arrangement is called master–slave.

Latches are smaller and faster, and transparent latches such as the 74HC373 are used to hold an address or data value while a bus carries something else. Flip-flops are easier to reason about in a system with feedback, which is why most synchronous designs use flip-flops and avoid latches.

Summary

Common mistakes

1. Using active-high thinking on a NAND latch. Its inputs act when they are 0; holding them at 0 is the invalid state, not the idle one.
2. Calling S = R = 1 a toggle. On a latch it is invalid. The toggling flip-flop is the JK, which is edge-triggered.
3. Expecting a latch to wait for an edge. A D latch passes every change of D while the enable is on.
4. Forgetting that the outputs are a pair. On the invalid input, Q and Q′ are equal, and any circuit that uses Q′ as “not Q” goes wrong.
5. Writing the latch equation without Q. The next state depends on the stored value, so Q has to appear as an input in the table and the equation.

Try it yourself

1. Write the latch as a next-state expression with Q as an input, for example NOR(R, NOR(S, Q)).
2. Open the truth table generator to see all eight rows, and compare it with a textbook equation such as S OR (NOT R AND Q) in the equivalence checker.
3. To test the allowed inputs only, check “allowed implies agree” for a tautology: NOT (S AND R) -> (NOR(R, NOR(S, Q)) <-> (S OR (NOT R AND Q))).

Frequently asked questions

What is the truth table of an SR latch?

For a NOR latch: S = 0, R = 0 holds; S = 0, R = 1 resets; S = 1, R = 0 sets; S = 1, R = 1 is invalid, with both outputs 0. A NAND latch has the same table with active-low inputs.

What is the truth table of a D latch?

With the enable at 0 the latch holds; with the enable at 1, Q follows D. Its equation is Q+ = E·D + E′·Q.

Why is S = R = 1 not allowed in an SR latch?

Both outputs become 0 in a NOR latch, so they are no longer opposites, and when S and R return to 0 together the latch falls into an unpredictable state.

What is the difference between a NOR and a NAND SR latch?

The NOR latch has active-high inputs and its invalid state has both outputs at 0. The NAND latch has active-low inputs and its invalid state has both outputs at 1.

What is the difference between a latch and a flip-flop?

A latch follows its inputs for as long as its enable is active; a flip-flop changes only at a clock edge.

Why is the D latch called transparent?

Because while its enable is on, the data input passes straight through to the output, as if the latch were not there.

How does a D latch avoid the invalid state?

It derives S and R from one input, S = D and R = D′, so they can never both be 1.

Related pages

• Guides: flip-flop truth tables
• Operators: NOR and NAND
• Glossary: combinational logic, which latches are not, and universal gate
• The consensus theorem, behind the glitch-free D latch
• 2-to-1 multiplexer, the D latch's logic without the feedback
• Don't-care conditions, as used for S = R = 1 in the textbook equation

Written by Muaz Notiar. The Tangibool engine (semantics tangibool-semantics/1, engine 1.0.0) computed the 3 truth tables marked “Computed by the Tangibool engine”, and the 11 tool results the guide links to were re-run through the tools' own code in the build of 2026-11-07 and match what the text says. © 2026 Foreranger LTD.