Flip-flop truth tables: SR, JK, D and T flip-flops with characteristic and excitation tables

By Muaz Notiar, founder of Tangibool Published 7 November 2026 14 min read

A flip-flop stores one bit and changes it only on a clock edge. Its truth table gives the next state Q+ from the inputs and the present state Q: an SR flip-flop sets or resets, a JK also toggles when J = K = 1, a D copies its input, and a T toggles when T = 1.

This guide gives each of the four types with its symbol, its truth table (the characteristic table), its characteristic equation and its excitation table. It derives each equation with a Karnaugh map, explains edge triggering and the master–slave flip-flop, and shows how to turn one type into another. The equations are checked by the Tangibool engine, which treats the present state Q as one more input. The tools work on the logic only: they do not simulate clocks, delays or timing.

The four flip-flops at a glance

Q+ is the state after the clock edge. Books also write it Q(t+1), Qn+1 or Q*. Q′ is NOT Q, and every flip-flop also has an output Q′ (drawn as Q with a bar over it) that is always the opposite of Q.

How to read a flip-flop truth table

A logic gate's output depends only on its inputs. A flip-flop's next state depends on its inputs and on what it is storing now, so its tables have the present state Q as an extra column. Three descriptions are used, and they say the same thing in different directions:

• The characteristic table answers “given these inputs and this state, what is the next state?”. It is what people mean by the truth table of a flip-flop. The short form lists only the inputs, with Q and Q′ in the output column. The long form has Q as an input column and one row for each combination.
• The characteristic equation writes Q+ as a Boolean expression in the inputs and Q. It is read off the long table with a Karnaugh map, like any other function.
• The excitation table runs the other way: “to go from this Q to that Q+, what inputs do I need?”. It is the table used to design counters and other state machines.

The change happens only at the active edge of the clock, the moment the clock goes from 0 to 1 (a rising edge) or from 1 to 0 (a falling edge). Between edges the flip-flop holds its state whatever the inputs do. On a symbol, a small triangle at the clock input marks edge triggering, and a bubble in front of it means the falling edge.

SR flip-flop

The SR flip-flop has a set input S and a reset input R. Its symbol is a box with S, R and the clock on the left and Q and Q′ on the right.

SR flip-flop truth table

With Q as an input, the table has eight rows. The first column marks the rows the flip-flop may receive, the second is the table above with the not-allowed rows left at 0, and the third is the characteristic equation:

Computed by the Tangibool engine

On rows 0 to 5 the table and the equation agree. Rows 6 and 7 have S = R = 1. The flip-flop must never receive them, so the specification says nothing there, and the equation is free to give anything.

SR characteristic equation

Put the table on a Karnaugh map with S down the side and R Q across the top. The 1s are minterms 1, 4 and 5, and cells 6 and 7, where S = R = 1, are don't-cares: cells that may be treated as 0 or 1, whichever makes larger groups. Treating both as 1 lets the whole S = 1 row form a group of four, which is just S. Minterms 1 and 5 form a pair, R′Q. So

Q+ = S + R′Q

In words: the next state is 1 if you set it, or if it was already 1 and you did not reset it.

The free Karnaugh map solver maps the function as written, and a minterm list has no way to mark don't-cares, so it reads cells 6 and 7 as 0. It then groups the 1s as S·R′ + R′·Q, which is R′(S + Q). That is also a correct characteristic equation, one that resets when S = R = 1 instead of setting. Both agree with the table on every row the flip-flop may receive: the truth table generator shows that “if not both S and R, then the two equations agree” is true on all eight rows, and that “if not both S and R, then S + R′Q matches the table” is too. Without the “if”, the equivalence checker finds them different, with the counterexample S = T, R = T, Q = F: a not-allowed row, as expected.

SR excitation table

X means “either value”. To keep a 0, do not set it (R does not matter). To keep a 1, do not reset it.

Why S = R = 1 is not allowed

Inside, an SR flip-flop is built on a latch of two cross-coupled NOR or NAND gates. With S = R = 1 on a NOR latch, both outputs are forced to 0, so Q and Q′ are no longer opposites. Worse, when S and R return to 0 together, the latch falls into whichever state the faster gate wins, which cannot be predicted. Designs avoid the input altogether, which is what the JK flip-flop does.

JK flip-flop

The JK flip-flop is the SR flip-flop with the forbidden case put to use: J acts as set, K as reset, and J = K = 1 toggles the output.

JK flip-flop truth table

With Q as an input, and the characteristic equation beside it:

Computed by the Tangibool engine

The two columns match on every row; the equivalence checker confirms it.

JK characteristic equation

On the map with J down the side and K Q across the top, the 1s are minterms 1, 4, 5 and 6, and there are no don't-cares. The Karnaugh map solver groups them as two pairs: J·Q′ (minterms 4 and 6) and K′·Q (minterms 1 and 5). So

Q+ = JQ′ + K′Q

In words: a stored 0 becomes 1 when J is 1, and a stored 1 stays 1 unless K is 1. With J = K = 1 the equation becomes 1·Q′ + 0·Q, which is Q′: the toggle.

JK excitation table

The JK has more X entries than any other type, which is why it was the usual choice for counters designed by hand: more don't-cares give smaller logic in front of the flip-flops.

The race-around problem

In a JK built on a level-triggered latch, J = K = 1 makes the output toggle, the new output feeds back to the inputs, and the output toggles again, for as long as the clock stays high. The output then ends up in a state that depends on how long the clock pulse lasted. Edge triggering and the master–slave construction both fix it, because the output can change only once per clock cycle.

D flip-flop

The D flip-flop has one data input. At the clock edge, Q takes the value of D, and holds it until the next edge. D stands for data, or for delay, since the output is the input delayed by one clock cycle.

D flip-flop truth table

With Q as an input, the present state makes no difference:

Computed by the Tangibool engine

The characteristic equation is Q+ = D, and the equivalence checker agrees with the table on all four rows. The excitation table is just as simple: to reach Q+, put D = Q+.

The D flip-flop is the workhorse of digital design. A register is a row of D flip-flops sharing a clock, a shift register is a chain of them, each feeding the next, and a pipeline stage in a processor is a register between two blocks of logic. Most designs use D flip-flops and put any JK or T behaviour into the logic in front of them.

Master–slave D flip-flop

A master–slave D flip-flop is two D latches in series. A D latch is transparent, its output following D, while its enable is 1, and holds while it is 0. The master latch is enabled while the clock is 0 and the slave while the clock is 1. So while the clock is low, the master follows D and the slave holds the old output; when the clock rises, the master freezes the value D had at that moment and the slave passes it to Q. The pair behaves as a rising-edge flip-flop:

T flip-flop

The T flip-flop has one input: T = 1 toggles the output at the clock edge, and T = 0 holds it.

T flip-flop truth table

With Q as an input:

Computed by the Tangibool engine

T characteristic equation

The map has two 1s on a diagonal, minterms 1 and 2, which cannot be grouped. The Karnaugh map solver gives T′Q + TQ′, and that pattern is XOR: Q+ = T ⊕ Q, which the equivalence checker confirms against the table. The excitation table follows from the equation: T = Q ⊕ Q+, so T is 1 exactly when the state has to change.

A T flip-flop with T tied to 1 toggles on every clock edge, so its output is a clock at half the frequency. Chain several, each clocked by the output of the one before, and you have a binary ripple counter: each stage halves the frequency again, and together the outputs step through the binary numbers, up or down depending on which clock edge the flip-flops use.

Excitation tables side by side

For counter and state-machine design, the four excitation tables are usually printed together:

To design a counter: list each state and the state that must follow it, look up the inputs each flip-flop needs for its transition, and simplify each input as a function of the present state, with the X entries as don't-cares.

Edge triggering, latches and timing

• Latch or flip-flop. A latch is level-sensitive: while its enable is active, the output follows the inputs. A flip-flop is edge-triggered: it samples its inputs at one instant per clock cycle. Many books say “SR flip-flop” for both; the difference matters as soon as outputs feed back to inputs.
• Rising or falling edge. A positive-edge flip-flop changes on the clock's rise and a negative-edge one on its fall; the bubble at the clock input marks the second.
• Setup and hold time. The inputs must be stable for a short time before the edge (setup) and after it (hold). If D changes inside that window, the flip-flop can become metastable and take an unpredictable time to settle.
• Preset and clear. Many flip-flops also have asynchronous inputs that force Q to 1 (preset) or 0 (clear) at once, without waiting for the clock. They are often active-low, drawn with a bubble.

The truth tables in this guide describe what the state becomes at the edge. Setup and hold times, delays and metastability are electrical behaviour, outside what a truth table, or Tangibool's tools, can show.

Converting one flip-flop into another

To make flip-flop X behave like flip-flop Y, drive X's inputs with logic that gives Y's characteristic equation. Either substitute and simplify, or use X's excitation table.

• JK to T. Tie J and K together and call the input T. The equation becomes TQ′ + T′Q, which is T ⊕ Q, the T flip-flop.
• JK to D. Connect J = D and K = D′. The equation becomes DQ′ + DQ, which is D.
• D to T. Feed D = T ⊕ Q, an XOR of the T input and the present output. Then Q+ = D = T ⊕ Q, which written out is T′Q + TQ′.
• T to D. Feed T = D ⊕ Q. Then Q+ = T ⊕ Q = (D ⊕ Q) ⊕ Q, which is D, because Q ⊕ Q cancels.
• SR to JK. Feed S = JQ′ and R = KQ. Substituting into Q+ = S + R′Q gives JQ′ + (KQ)′Q, which is JQ′ + K′Q. It also never sends S = R = 1, because JQ′ and KQ can never both be 1: one needs Q = 0, the other Q = 1.

Summary

Common mistakes

1. Reading S = R = 1 as toggle. That is the JK flip-flop. On an SR flip-flop it is not allowed.
2. Mixing up the characteristic and excitation tables. The first gives the next state from the inputs, the second gives the inputs from the change of state. Counter design needs the second.
3. Writing the JK equation as J + K′Q. It gives 1 when J = K = 1 and Q = 1, where the flip-flop toggles to 0. The equivalence checker finds that row: J = T, K = T, Q = T.
4. Expecting the output to change between clock edges. A flip-flop's output changes only at the active edge (or when preset or clear is used); a latch is the one that follows its inputs.
5. Forgetting Q in the table. Without the present state as a column, the hold and toggle rows cannot be written as a Boolean function, and a Karnaugh map cannot be drawn.

Try it yourself

1. Write the long characteristic table as a list of minterms, with the inputs first and Q last, for example Σm(J, K, Q; 1, 4, 5, 6) for the JK.
2. Paste it into the Karnaugh map solver to see the groups and the equation.
3. Compare the equation with the table in the equivalence checker. For the SR flip-flop, check “allowed implies agree” in the truth table generator, for example NOT (S AND R) -> (Σm(S, R, Q; 1, 4, 5) <-> (S OR (NOT R AND Q))), and look for a tautology.

Frequently asked questions

What is the truth table of a JK flip-flop?

J = 0, K = 0 holds the state; J = 0, K = 1 resets it to 0; J = 1, K = 0 sets it to 1; and J = 1, K = 1 toggles it. The characteristic equation is Q+ = JQ′ + K′Q.

What is the truth table of a D flip-flop?

At the clock edge the output takes the value of D: D = 0 gives Q+ = 0 and D = 1 gives Q+ = 1. The equation is Q+ = D.

What is the truth table of a T flip-flop?

T = 0 holds the state and T = 1 toggles it. The equation is Q+ = T ⊕ Q.

What is the truth table of an SR flip-flop?

S = 0, R = 0 holds; S = 0, R = 1 resets; S = 1, R = 0 sets; S = 1, R = 1 is not allowed. The equation is Q+ = S + R′Q, using S = R = 1 as a don't-care.

Why is S = R = 1 not allowed in an SR flip-flop?

It drives both outputs to the same value, and when both inputs return to 0 the final state is unpredictable.

What is a characteristic equation?

The next state Q+ written as a Boolean expression in the inputs and the present state Q, read off the characteristic table with a Karnaugh map.

What is an excitation table?

A table that gives, for each change from Q to Q+, the inputs a flip-flop needs to make it. Counter design uses it.

What does Q(t+1) mean?

The state of the flip-flop after the next clock edge. Q(t), or Q, is the state now.

What is the difference between a latch and a flip-flop?

A latch follows its inputs for as long as its enable is active; a flip-flop changes only at a clock edge.

How do you convert a JK flip-flop to a T flip-flop?

Connect J and K together and use the joined input as T. With J = K = T the equation JQ′ + K′Q becomes T ⊕ Q.

What is a master–slave flip-flop?

Two latches in series, enabled on opposite halves of the clock, so the output changes only once per cycle, at the clock edge.

Related pages

• Guides: SR latch and D latch
• Karnaugh maps, Lesson 11, the Karnaugh map solver and don't-care conditions
• Combinational logic, which flip-flops are not: their outputs depend on the state as well as the inputs
• XOR, the operator of the T flip-flop
• Minterms and the minterm expansion, the Σm notation used above
• Practice: Karnaugh maps with 3 variables, with answers

Written by Muaz Notiar. The Tangibool engine (semantics tangibool-semantics/1, engine 1.0.0) computed the 4 truth tables marked “Computed by the Tangibool engine”, and the 17 tool results the guide links to were re-run through the tools' own code in the build of 2026-11-07 and match what the text says. © 2026 Foreranger LTD.