Half subtractor and full subtractor: truth tables, borrow logic, K-maps and circuits
A half subtractor computes A − B for two bits: the difference is A XOR B and the borrow is A′·B, which is 1 only for 0 − 1. A full subtractor also subtracts a borrow-in, so it can be chained: its difference is A XOR B XOR Bin, and its borrow-out is A′B + A′Bin + B·Bin.
This guide gives both truth tables, derives the equations with Karnaugh maps, builds a full subtractor from two half subtractors, wires both circuits from NAND gates only, and shows the 4-bit adder–subtractor that real processors use. A one-page summary sits near the end. The truth tables are computed by the Tangibool engine, and every claim that two circuits are the same links to a free checker that tests them on every row.
Subtracting binary numbers, one column at a time
Binary subtraction works column by column from the right, like decimal subtraction. When the top bit is smaller than the bottom bit, the column borrows 1 from the column to its left, which is worth 2 in this column. For one column of two bits there are four cases:
| A − B | Result | Difference bit | Borrow |
|---|---|---|---|
| 0 − 0 | 0 | 0 | 0 |
| 0 − 1 | borrow 2, then 2 − 1 = 1 | 1 | 1 |
| 1 − 0 | 1 | 1 | 0 |
| 1 − 1 | 0 | 0 | 0 |
Every column after the first must also subtract the borrow that the column to its right took, so it handles three bits: A − B − Bin. A circuit for two bits is a half subtractor; a circuit for three is a full subtractor.
Half subtractor
Truth table
T stands for 1 and F for 0, and row 0 has both inputs at 0:
| # | A | B | difference | borrow |
|---|---|---|---|---|
| 0 | FALSE | FALSE | FALSE | FALSE |
| 1 | FALSE | TRUE | TRUE | TRUE |
| 2 | TRUE | FALSE | TRUE | FALSE |
| 3 | TRUE | TRUE | FALSE | FALSE |
Computed by the Tangibool engine
Equations and circuit
- Difference: D = A ⊕ B, one XOR gate. It is 1 when the bits differ, exactly as the sum of a half adder.
- Borrow: Bout = A′·B, a NOT gate on A and an AND gate. It is 1 only on row 1, 0 − 1.
So a half subtractor is a half adder with one change: the AND gate that makes the borrow takes A inverted. Mixing the two up is the most common mistake; A′·B and A·B′ are different, and the checker gives the row A = F, B = T, which is 0 − 1, the one case that borrows.
Half subtractor from NAND gates
Five NAND gates are enough. The first four are the classic NAND XOR, NAND(NAND(A, NAND(A, B)), NAND(B, NAND(A, B))), which gives the difference. Its third gate, NAND(B, NAND(A, B)), happens to compute NOT (A′·B), the inverted borrow, so a fifth NAND that inverts it gives the borrow.
Full subtractor
Truth table
A full subtractor has three inputs, A, B and the borrow-in Bin from the column to its right, and two outputs, the difference D and the borrow-out Bout. Read each row as A − B − Bin:
| # | A | B | Bin | A ⊕ B | difference | Bout |
|---|---|---|---|---|---|---|
| 0 | FALSE | FALSE | FALSE | FALSE | FALSE | FALSE |
| 1 | FALSE | FALSE | TRUE | FALSE | TRUE | TRUE |
| 2 | FALSE | TRUE | FALSE | TRUE | TRUE | TRUE |
| 3 | FALSE | TRUE | TRUE | TRUE | FALSE | TRUE |
| 4 | TRUE | FALSE | FALSE | TRUE | TRUE | FALSE |
| 5 | TRUE | FALSE | TRUE | TRUE | FALSE | FALSE |
| 6 | TRUE | TRUE | FALSE | FALSE | FALSE | FALSE |
| 7 | TRUE | TRUE | TRUE | FALSE | TRUE | TRUE |
Computed by the Tangibool engine
Row 3 is 0 − 1 − 1 = −2: the column borrows 2, leaving 0, so D = 0 and Bout = 1. Row 7 is 1 − 1 − 1 = −1: borrow 2, leaving 1, so D = 1 and Bout = 1. The difference is 1 on rows 1, 2, 4 and 7, and the borrow-out on rows 1, 2, 3 and 7.
The difference: an XOR, like the adder's sum
The difference column, Σm(1, 2, 4, 7), is the same as a full adder's sum. Its Karnaugh map is a checkerboard: every 1 is surrounded by 0s, so the Karnaugh map solver can only circle each 1 on its own. That pattern is three-input XOR, D = A ⊕ B ⊕ Bin, and the equivalence checker confirms it on all eight rows.
The borrow-out
The borrow-out's 1s, minterms 1, 2, 3 and 7, form three overlapping pairs on the map (A down the side, B Bin across the top). The Karnaugh map solver circles them as A′·B, A′·Bin and B·Bin, so
Bout = A′·B + A′·Bin + B·Bin
and the equivalence checker confirms it against the table. In words, the column borrows when B alone is more than A (A′·B), when the borrow-in alone is more than A (A′·Bin), or when B and the borrow-in together are more than any single bit (B·Bin).
Compare it with a full adder's carry-out, A·B + A·Cin + B·Cin: the borrow-out is the same majority function with A inverted.
Full subtractor from two half subtractors
- The first half subtractor computes A − B: its difference is A ⊕ B and its borrow is A′·B.
- The second half subtractor subtracts Bin from that difference: its difference is A ⊕ B ⊕ Bin, the full subtractor's difference, and its borrow is (A ⊕ B)′·Bin.
- An OR gate combines the two borrows.
So Bout = A′·B + (A ⊕ B)′·Bin, and the equivalence checker shows it is the same as the three-term form. The column A ⊕ B in the truth table is the first half subtractor's difference, and the truth table generator draws this form of the borrow-out circuit.
Two details:
- The second borrow uses the complement of A ⊕ B. Writing (A ⊕ B)·Bin instead is a common slip, and the checker finds the row A = F, B = F, Bin = T: 0 − 0 − 1 borrows, but the slip says it does not.
- The OR could be an XOR. The two half-subtractor borrows are never 1 together, so replacing the OR with an XOR gives the same borrow-out.
Full subtractor circuit, gate by gate
| Gate | Type | Inputs | Output | Part of |
|---|---|---|---|---|
| G1 | XOR | A, B | A ⊕ B | first half subtractor (difference) |
| G2 | NOT | A | A′ | first half subtractor |
| G3 | AND | G2, B | A′·B | first half subtractor (borrow) |
| G4 | XOR | G1, Bin | difference | second half subtractor (difference) |
| G5 | NOT | G1 | (A ⊕ B)′ | second half subtractor |
| G6 | AND | G5, Bin | (A ⊕ B)′·Bin | second half subtractor (borrow) |
| G7 | OR | G3, G6 | Bout | combines the borrows |
NAND-only full subtractor: nine gates
As with the full adder, nine NAND gates are enough when the sum and borrow share gates:
| Gate | Output | What it computes |
|---|---|---|
| 1 | n1 = NAND(A, B) | |
| 2 | n2 = NAND(A, n1) | |
| 3 | n3 = NAND(B, n1) | NOT (A′·B), the first inverted borrow |
| 4 | x = NAND(n2, n3) | A ⊕ B |
| 5 | n5 = NAND(x, Bin) | |
| 6 | n6 = NAND(x, n5) | |
| 7 | n7 = NAND(Bin, n5) | NOT ((A ⊕ B)′·Bin), the second inverted borrow |
| 8 | D = NAND(n6, n7) | A ⊕ B ⊕ Bin |
| 9 | Bout = NAND(n3, n7) | A′·B + (A ⊕ B)′·Bin |
The only difference from the nine-gate full adder is where the borrow is taken: gates 3 and 7, not gates 1 and 5, because the borrow needs the inputs the other way round. Written out as expressions the gates repeat, but the checks still run: the difference and the borrow-out both match the truth table.
Subtracting with an adder: two's complement
Processors rarely contain a separate subtractor. In two's complement arithmetic, A − B = A + B′ + 1: invert every bit of B and add 1. So an adder subtracts if B is inverted on its way in and the first carry-in is set to 1.
A full subtractor is exactly a full adder with B inverted and the borrows inverted: carry means “no borrow”. Feeding B′ and Bin′ into a full adder gives the sum A ⊕ B′ ⊕ Bin′, which is the subtractor's difference, because the two inversions cancel. The adder's carry-out, inverted, is the subtractor's borrow-out. That is why some processors store the carry after a subtraction and others store its inverse as a borrow flag.
The 4-bit adder–subtractor
One circuit does both. Add a mode line M and four XOR gates:
- Each bit of B passes through an XOR gate with M before it reaches its full adder. When M = 0, B ⊕ 0 = B; when M = 1, B ⊕ 1 = B′.
- M is also the carry-in of the first full adder.
So M = 0 computes A + B, and M = 1 computes A + B′ + 1 = A − B, with four full adders and four XOR gates in total.
Example: 7 − 2 with M = 1. B = 0010 becomes 1101, and 0111 + 1101 + 1 = 1 0101. The lower four bits, 0101, are 5, and the carry-out of 1 means no borrow. Example: 2 − 7. B = 0111 becomes 1000, and 0010 + 1000 + 1 = 1011, with a carry-out of 0. Read as a signed 4-bit number, 1011 is −5; the carry-out of 0 says that a borrow was needed.
A 4-bit ripple-borrow subtractor
Chaining four full subtractors also works: each borrow-out feeds the next column's borrow-in, and the first borrow-in is 0. For 1001 − 0011 (9 − 3):
| Column | A | B | Borrow in | Difference | Borrow out |
|---|---|---|---|---|---|
| 0 (rightmost) | 1 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 2 | 0 | 0 | 1 | 1 | 1 |
| 3 | 1 | 0 | 1 | 0 | 0 |
The differences, from column 3 down to column 0, read 0110, which is 6. Column 1 borrows from column 2, and column 2, having nothing, borrows from column 3.
Summary sheet
| Circuit | Inputs | Outputs | Equations | Gates |
|---|---|---|---|---|
| Half subtractor | A, B | D, Bout | D = A ⊕ B, Bout = A′·B | 1 XOR, 1 NOT, 1 AND |
| Half subtractor, NAND only | A, B | D, Bout | as above | 5 NAND |
| Full subtractor | A, B, Bin | D, Bout | D = A ⊕ B ⊕ Bin, Bout = A′B + A′Bin + B·Bin = A′B + (A ⊕ B)′·Bin | 2 XOR, 2 NOT, 2 AND, 1 OR |
| Full subtractor, NAND only | A, B, Bin | D, Bout | as above | 9 NAND |
| 4-bit adder–subtractor | A3…A0, B3…B0, M | S3…S0, C4 | B ⊕ M into each full adder, carry-in M | 4 full adders, 4 XOR |
Half subtractor vs half adder: the outputs are A ⊕ B in both; the second output is A′·B for the borrow and A·B for the carry. Full subtractor vs full adder: the difference and the sum are both A ⊕ B ⊕ (third input); the borrow-out is the carry-out's majority function with A inverted.
Common mistakes
- Borrow = A·B′. That is “A greater than B”, the opposite case. The borrow is A′·B: 0 − 1.
- Using A ⊕ B in the second borrow. It must be the complement, (A ⊕ B)′·Bin: a borrow-in causes a borrow-out when A and B are equal.
- Treating the difference as different from the adder's sum. They are the same function, A ⊕ B ⊕ third input.
- Forgetting the first borrow-in. In a ripple-borrow subtractor it is 0; in an adder–subtractor the first carry-in is M, which is 1 when subtracting.
- Reading the final carry of A + B′ + 1 as an overflow. In subtraction it means “no borrow”. Signed overflow is a separate check, on the carries into and out of the last column.
Try it yourself
- Type an output into the truth table generator, for example
(NOT A AND B) OR (NOT A AND Bin) OR (B AND Bin), to see its eight rows and the gates. - Type the borrow-out's minterms,
Σm(A, B, Bin; 1, 2, 3, 7), into the Karnaugh map solver to see the three pairs. - Check a design of your own, such as a NAND-only borrow, against the three-term form in the equivalence checker.
Frequently asked questions
What is a half subtractor?
A circuit that subtracts one bit from another and outputs a difference, A ⊕ B, and a borrow, A′·B.
What is a full subtractor?
A circuit that computes A − B − Bin for three bits and outputs a difference, A ⊕ B ⊕ Bin, and a borrow-out, A′B + A′Bin + B·Bin.
What is the difference between a half subtractor and a full subtractor?
A full subtractor has a borrow-in and a half subtractor does not, so only full subtractors can be chained for numbers of more than one bit.
How many half subtractors make a full subtractor?
Two, plus an OR gate that combines their borrows.
What is the truth table of a full subtractor?
Eight rows for A, B and Bin. The difference is 1 on rows 1, 2, 4 and 7, and the borrow-out on rows 1, 2, 3 and 7.
How many NAND gates does a full subtractor need?
Nine, with the difference and the borrow sharing gates; a half subtractor needs five.
What is the difference between a half adder and a half subtractor?
Both output A ⊕ B. The half adder's second output is the carry, A·B; the half subtractor's is the borrow, A′·B.
How does a 4-bit adder–subtractor work?
An XOR gate on each B input inverts B when the mode line M is 1, and M is also the first carry-in, so the adders compute A + B′ + 1, which is A − B in two's complement.
Related pages
- Guides: half adder and full adder
- XOR and three-input XOR is parity
- Worked examples: half adder sum, full adder sum, full adder carry, majority of three, XOR from four NAND gates
- Karnaugh maps: Lesson 11 and the Karnaugh map solver
- Combinational logic and universal gates
- Practice: NAND-only design, with answers
Written by Muaz Notiar. The Tangibool engine (semantics tangibool-semantics/1, engine 1.0.0) computed the 2 truth tables marked “Computed by the Tangibool engine”, and the 15 tool results the guide links to were re-run through the tools' own code in the build of and match what the text says. © 2026 Foreranger LTD.