Half adder and full adder: truth tables, K-maps, circuits, and a full adder from two half adders
A half adder adds two bits and outputs a sum and a carry: sum = A XOR B, carry = A AND B. A full adder also takes a carry-in, so it can be chained: its sum is A XOR B XOR Cin, and its carry-out is 1 when at least two of its three inputs are 1.
This guide gives the truth table of each, explains the equations with Karnaugh maps, builds a full adder from two half adders and an OR gate, wires it from NAND gates only, and chains four full adders into a 4-bit adder. The truth tables are computed by the Tangibool engine, and every claim that two circuits are the same links to a free checker that tests them on every row.
Adding binary numbers, one column at a time
Binary addition works like decimal addition, column by column from the right, carrying when a column overflows. In one column there are only four cases for two bits:
| A + B | Decimal | Sum bit | Carry |
|---|---|---|---|
| 0 + 0 | 0 | 0 | 0 |
| 0 + 1 | 1 | 1 | 0 |
| 1 + 0 | 1 | 1 | 0 |
| 1 + 1 | 2, binary 10 | 0 | 1 |
The sum bit is the right-hand digit of the answer and the carry is the left-hand digit, which moves to the next column. Every column after the first also receives a carry from the column before, so it adds three bits: 1 + 1 + 1 is 3, binary 11, a sum bit of 1 and a carry of 1. A circuit for the first case is a half adder. A circuit for the three-bit case is a full adder.
Half adder
Truth table
T stands for 1 and F for 0, and row 0 has both inputs at 0:
| # | A | B | sum | carry |
|---|---|---|---|---|
| 0 | FALSE | FALSE | FALSE | FALSE |
| 1 | FALSE | TRUE | TRUE | FALSE |
| 2 | TRUE | FALSE | TRUE | FALSE |
| 3 | TRUE | TRUE | FALSE | TRUE |
Computed by the Tangibool engine
The sum column is 1 when exactly one input is 1, which is XOR. The carry column is 1 only when both inputs are 1, which is AND.
Equations and circuit
- Sum: S = A ⊕ B, one XOR gate. Written with AND, OR and NOT it is (A AND NOT B) OR (NOT A AND B).
- Carry: C = A · B, one AND gate.
So a half adder is two gates side by side, an XOR and an AND, both fed by A and B. The half adder sum page shows both outputs with their table, map and diagram, and the carry page does the same from the carry's side.
It is called a half adder because it does half the job of one column of a multi-bit adder: it has no input for the carry from the column before. It can only be used for the rightmost column, where there is no carry in.
Half adder from NAND gates
Since NAND is a universal gate, a half adder can be built from NAND gates alone, with five of them. The XOR is the classic four-NAND circuit, NAND(NAND(A, NAND(A, B)), NAND(B, NAND(A, B))). Its first gate, NAND(A, B), is already the inverted carry, so one more NAND that inverts it gives the carry: NAND(NAND(A, B), NAND(A, B)) is A AND B. The worked example of XOR from four NAND gates goes through the first part gate by gate.
Full adder
Truth table
A full adder has three inputs, A, B and the carry-in Cin, and two outputs, the sum and the carry-out Cout. Three inputs give eight rows. The first column below is the sum of the first two bits alone, which the next section uses:
| # | A | B | Cin | A ⊕ B | sum | Cout |
|---|---|---|---|---|---|---|
| 0 | FALSE | FALSE | FALSE | FALSE | FALSE | FALSE |
| 1 | FALSE | FALSE | TRUE | FALSE | TRUE | FALSE |
| 2 | FALSE | TRUE | FALSE | TRUE | TRUE | FALSE |
| 3 | FALSE | TRUE | TRUE | TRUE | FALSE | TRUE |
| 4 | TRUE | FALSE | FALSE | TRUE | TRUE | FALSE |
| 5 | TRUE | FALSE | TRUE | TRUE | FALSE | TRUE |
| 6 | TRUE | TRUE | FALSE | FALSE | FALSE | TRUE |
| 7 | TRUE | TRUE | TRUE | FALSE | TRUE | TRUE |
Computed by the Tangibool engine
Read each row as an addition. Row 7 is 1 + 1 + 1 = 3, binary 11: sum 1, carry-out 1. Row 3 is 0 + 1 + 1 = 2, binary 10: sum 0, carry-out 1. The sum is 1 on rows 1, 2, 4 and 7, where an odd number of inputs are 1, and the carry-out is 1 on rows 3, 5, 6 and 7, where at least two are.
The sum: a Karnaugh map that will not group
A Karnaugh map arranges the eight rows so that neighbouring cells differ in one input. The usual layout has A down the side and B Cin across the top in the Gray-code order 00, 01, 11, 10. Simplifying means circling neighbouring 1s in groups of two, four or eight; each group drops the input that changes inside it.
The sum's four 1s, minterms 1, 2, 4 and 7, land in a checkerboard: every 1 is surrounded by 0s, so no two 1s can be grouped. The Karnaugh map solver draws the map and can only circle each 1 on its own, so the sum of products keeps all four three-input terms: (¬A ∧ ¬B ∧ Cin) ∨ (¬A ∧ B ∧ ¬Cin) ∨ (A ∧ ¬B ∧ ¬Cin) ∨ (A ∧ B ∧ Cin).
A checkerboard is the signature of XOR. Changing any one input always changes the output, which is exactly why no two 1s sit side by side. So the sum is written with XOR gates: S = A ⊕ B ⊕ Cin, two XOR gates instead of four three-input ANDs and an OR. A chain of XORs is 1 when an odd number of its inputs are 1, which matches the addition: 1 + 1 + 1 gives a sum bit of 1. That is also why the sum is not “exactly one input is 1”; the equivalence checker gives the row where those differ, A = B = Cin = T.
The carry-out: the majority function
The carry-out's 1s, minterms 3, 5, 6 and 7, sit together: the three cells next to the all-1s cell, and that cell itself. The Karnaugh map solver covers them with three overlapping pairs, A·B, A·Cin and B·Cin, so
Cout = A·B + A·Cin + B·Cin
which is 1 whenever at least two inputs are 1. That is the majority-of-three function, the same function as a two-out-of-three vote. The three pairs overlap in the all-1s cell, and a K-map is allowed to cover a cell more than once.
Many textbooks write the carry-out another way, Cout = A·B + Cin·(A ⊕ B): either both operand bits are 1, or exactly one is and the carry-in is 1. The equivalence checker shows the two forms are the same on all eight rows. The second form costs more gates on its own, but in a full adder the XOR is already there, because the sum needs A ⊕ B.
Full adder from two half adders and an OR gate
The two forms of the carry show how to build a full adder from parts you already have:
- The first half adder adds A and B. Its sum is A ⊕ B, and its carry is A·B.
- The second half adder adds that sum and Cin. Its sum is A ⊕ B ⊕ Cin, the full adder's sum. Its carry is Cin·(A ⊕ B).
- An OR gate combines the two carries: Cout = A·B + Cin·(A ⊕ B).
That is two half adders and one OR gate, five gates in all: two XOR, two AND and one OR. The column A ⊕ B in the truth table above is the first half adder's sum. Wired gate by gate, the full adder circuit is:
| Gate | Type | Inputs | Output | Part of |
|---|---|---|---|---|
| G1 | XOR | A, B | A ⊕ B | first half adder (sum) |
| G2 | AND | A, B | A·B | first half adder (carry) |
| G3 | XOR | G1, Cin | sum | second half adder (sum) |
| G4 | AND | G1, Cin | Cin·(A ⊕ B) | second half adder (carry) |
| G5 | OR | G2, G4 | Cout | combines the carries |
In a circuit diagram A and B enter on the left, G1 and G2 sit side by side, G3 and G4 take G1's output with Cin, and G5 joins the two carries on the right. The truth table generator draws the carry-out part from its formula, and the full adder carry page has its normal forms.
Two details are worth knowing:
- The OR could be an XOR. The two half-adder carries are never 1 at the same time. If A and B are both 1, then A ⊕ B is 0, so the second carry is 0. That makes OR and XOR give the same answer here, and A·B ⊕ Cin·(A ⊕ B) is also the carry-out.
- The inner XOR could be an OR. For the carry alone, A·B + Cin·(A + B) also works, because the case it adds, A and B both 1, is already covered by A·B. Carry-lookahead adders use this freedom, as the section on speed shows.
NAND-only full adder: nine gates
A full adder can also be built from NAND gates alone. A classic design uses nine, sharing gates between the sum and the carry. Name each gate's output:
| Gate | Output | What it computes |
|---|---|---|
| 1 | n1 = NAND(A, B) | NOT (A AND B) |
| 2 | n2 = NAND(A, n1) | |
| 3 | n3 = NAND(B, n1) | |
| 4 | x = NAND(n2, n3) | A ⊕ B |
| 5 | n5 = NAND(x, Cin) | NOT ((A ⊕ B) AND Cin) |
| 6 | n6 = NAND(x, n5) | |
| 7 | n7 = NAND(Cin, n5) | |
| 8 | sum = NAND(n6, n7) | A ⊕ B ⊕ Cin |
| 9 | Cout = NAND(n1, n5) | A·B + Cin·(A ⊕ B) |
Gates 1 to 4 are the four-NAND XOR of A and B, and gates 5 to 8 are the same circuit again for x and Cin. The carry needs only gate 9, because gates 1 and 5 already hold the two inverted carries, and a NAND of two inverted signals is their OR, by De Morgan's law.
Written out as expressions, the gates repeat, but the checks still run. The sum is equivalent to A ⊕ B ⊕ Cin, and the carry is equivalent to the majority form. The NAND and NOR converter produces a NAND-only full adder from any formula too, by mechanical rules; its construction is correct and checked, but it is longer than this hand-made one, because the rules do not look for gates to share.
4-bit ripple-carry adder
To add two 4-bit numbers A3A2A1A0 and B3B2B1B0, chain four full adders. Each one adds one column: its inputs are Ai, Bi and the carry from the column to its right, and its carry-out goes to the column on its left. The first carry-in, C0, is 0, or the first stage is a half adder. The last carry-out, C4, is the fifth bit of the answer.
Example: 6 + 7, that is 0110 + 0111.
| Column | A | B | Carry in | Sum bit | Carry out |
|---|---|---|---|---|---|
| 0 (rightmost) | 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
| 2 | 1 | 1 | 1 | 1 | 1 |
| 3 | 0 | 0 | 1 | 1 | 0 |
Reading the sum bits from column 3 down to column 0 gives 1101, which is 13. Column 2 is the full adder's busiest case, 1 + 1 + 1: sum 1, carry 1.
A second example overflows: 1011 + 0110 is 11 + 6 = 17. The four sum bits are 0001 and the final carry-out C4 is 1, giving 10001, which is 17. In a 4-bit register the carry-out has nowhere to go, so an unsigned result above 15 is an overflow that the carry-out flags.
Why “ripple”, and how adders go faster
In a ripple-carry adder each stage waits for the carry from the stage before, so the carry ripples from right to left. In the full adder above, the carry passes through an AND gate and an OR gate in each stage, so a 4-bit adder needs about 8 gate delays for the last carry, and a 64-bit one about 128.
Carry-lookahead adders compute the carries directly. For each column, the generate signal is g = A·B (this column makes a carry by itself) and the propagate signal is p = A ⊕ B or p = A + B (this column passes an incoming carry on). Then each carry is C(i + 1) = g(i) + p(i)·C(i), and expanding the recursion gives every carry from the inputs in a fixed number of gate levels. For a 2-bit adder with no carry-in, the carry out of column 1 is A1·B1 + p1·A0·B0, and the equivalence checker confirms that both choices of p give the same carry.
Subtraction with the same adder
A − B equals A + (NOT B) + 1 in two's complement arithmetic. So an adder becomes a subtractor by inverting each bit of B, which an XOR gate per bit does when a “subtract” line is 1, and by setting the first carry-in to 1. That is how most processors subtract.
Half adder vs full adder
| Half adder | Full adder | |
|---|---|---|
| Inputs | 2: A, B | 3: A, B, carry-in |
| Outputs | sum, carry | sum, carry-out |
| Sum | A ⊕ B | A ⊕ B ⊕ Cin |
| Carry | A·B | A·B + A·Cin + B·Cin |
| Gates in the usual design | 2 (XOR, AND) | 5 (2 XOR, 2 AND, OR) |
| NAND gates only | 5 | 9 |
| Can be chained for multi-bit addition | No, it has no carry-in | Yes |
| Typical use | the rightmost column, incrementers | every column of an adder |
Where adders are used
- The arithmetic logic unit (ALU). A processor's ALU adds, subtracts and compares with one adder and a few gates around it; comparing A and B is subtracting them and looking at the carry and the zero result.
- Counting up. Adding 1 to a number needs only half adders: start with a carry of 1, and in each column the sum is Ai ⊕ carry and the next carry is Ai·carry. Program counters and timers count this way.
- Multiplying. A binary multiplier forms a row of partial products with AND gates and adds the rows with arrays of full adders.
- Addresses and checksums. Computing the address of the next item in memory, or the checksum of a block of data, is addition.
In a hardware description language
In Verilog, a full adder is two lines: assign sum = a ^ b ^ cin; and assign cout = (a & b) | (cin & (a ^ b));, or the single statement assign {cout, sum} = a + b + cin;, which lets the synthesis tool choose the gates. Verilog writes XOR as ^ and AND as &. Tangibool's tools reject both, because the caret means a power in some languages and a single ampersand is bitwise in others, so type XOR and AND there. The pages on the caret and the single ampersand explain why.
Summary
| Circuit | Inputs | Outputs | Equations | Gates |
|---|---|---|---|---|
| Half adder | A, B | S, C | S = A ⊕ B, C = A·B | 1 XOR, 1 AND |
| Half adder, NAND only | A, B | S, C | as above | 5 NAND |
| Full adder | A, B, Cin | S, Cout | S = A ⊕ B ⊕ Cin, Cout = A·B + A·Cin + B·Cin = A·B + Cin·(A ⊕ B) | 2 XOR, 2 AND, 1 OR |
| Full adder, NAND only | A, B, Cin | S, Cout | as above | 9 NAND |
| 4-bit ripple-carry adder | A3…A0, B3…B0, C0 | S3…S0, C4 | four full adders, each carry-out to the next carry-in | 4 full adders |
Common mistakes
- Carry-out = A·B + Cin. It is 1 whenever Cin is 1, even for 0 + 0 + 1, which has no carry. The equivalence checker gives that row: A = F, B = F, Cin = T.
- Sum = A + B, using OR. OR gives 1 for 1 + 1, where the sum bit is 0 and the 1 belongs in the carry. The checker shows the row A = T, B = T.
- Reading the sum as “exactly one input is 1”. That misses row 7, 1 + 1 + 1, whose sum bit is 1.
- Forgetting the carry-in of the first stage. A ripple-carry adder whose C0 is left unconnected gives unpredictable answers. Tie it to 0 for addition, or to 1 for subtraction.
- Ignoring the final carry-out. In unsigned arithmetic it is the extra bit of the answer, or the overflow flag.
Try it yourself
- Open the truth table generator and type a full adder output, for example
(A AND B) OR (Cin AND (A XOR B)). It shows the eight rows and draws the gates. - Paste the same formula into the Karnaugh map solver to see the three pairs, or type the sum,
A XOR B XOR Cin, to see the checkerboard. - To check a design of your own, such as a NAND-only carry, put it and the majority form in the two boxes of the equivalence checker. If they differ, it shows an input row where they do.
NAND, NOR and XNOR are written as functions of two inputs: NAND(A, B). The tools also accept ⊕ for XOR and the algebra forms A·B and A + B.
Frequently asked questions
What is a half adder?
A circuit that adds two bits and outputs a sum bit, A XOR B, and a carry bit, A AND B. It is one XOR gate and one AND gate.
What is a full adder?
A circuit that adds three bits, two operand bits and a carry-in, and outputs a sum bit, A XOR B XOR Cin, and a carry-out, which is 1 when at least two inputs are 1.
What is the difference between a half adder and a full adder?
A full adder has a carry-in and a half adder does not. That is why full adders can be chained to add numbers of any length, while a half adder can only add the rightmost column.
Why is it called a half adder?
Because it does half of what one column of a multi-bit adder must do: it adds the two operand bits but cannot add the carry from the column before.
How many half adders make a full adder?
Two, plus an OR gate to combine their carries. The first adds A and B, and the second adds that sum and the carry-in.
What is the Boolean expression for a full adder?
Sum = A ⊕ B ⊕ Cin and Cout = A·B + A·Cin + B·Cin, which can also be written Cout = A·B + Cin·(A ⊕ B).
How many gates are in a full adder?
Five in the usual design: two XOR, two AND and one OR. Built from NAND gates only, it takes nine.
Why is the sum of a full adder an XOR?
Because its Karnaugh map is a checkerboard: changing any one input changes the sum, so no 1s can be grouped, and a function with that property is XOR or XNOR.
How many full adders does an n-bit adder need?
n for a ripple-carry adder, one per column, or n − 1 full adders and a half adder if the first column has no carry-in.
What is a ripple-carry adder?
A chain of full adders in which each stage's carry-out is the next stage's carry-in, so the carry travels, or ripples, from the rightmost column to the leftmost.
Related pages
- Guides: half subtractor and full subtractor
- Worked examples: half adder sum, half adder carry, full adder sum, full adder carry, majority of three, majority of three from NAND gates
- XOR and three-input XOR is parity
- Karnaugh maps: Lesson 11, grouping rules and the Karnaugh map solver
- Combinational logic and universal gates
- Practice: expressions to circuits and NAND-only design, with answers
Written by Muaz Notiar. The Tangibool engine (semantics tangibool-semantics/1, engine 1.0.0) computed the 2 truth tables marked “Computed by the Tangibool engine”, and the 16 tool results the guide links to were re-run through the tools' own code in the build of and match what the text says. © 2026 Foreranger LTD.