Multiplexer truth tables: 2-to-1, 4-to-1 and 8-to-1, with expressions and circuits

By Muaz Notiar, founder of Tangibool Published 7 November 2026 12 min read

A multiplexer, or mux, is a data selector: its select lines choose which of its data inputs reaches its one output. A 2-to-1 mux has one select line, a 4-to-1 has two and an 8-to-1 has three, and the 2-to-1 computes Y = S′·I0 + S·I1.

This guide gives the compact and full truth tables of the 2-to-1 and 4-to-1 multiplexers and the expressions for 2-, 4- and 8-to-1, builds bigger multiplexers from smaller ones, shows how a multiplexer computes any Boolean function, and ends with the demultiplexer. The truth tables are computed by the Tangibool engine, and each claim that two circuits do the same thing links to a free checker that tests them on every row.

What a multiplexer does

Picture a rotary switch with several inputs and one output: turning the knob connects one input to the output. A multiplexer is that switch built from logic gates, with the knob replaced by select lines. With n select lines there are 2ⁿ positions, so a mux with n select lines has 2ⁿ data inputs:

The select lines, read as a binary number, give the number of the input that is passed through: S1 S0 = 10 is 2, so a 4-to-1 mux outputs I2. In circuit diagrams a mux is drawn as a trapezoid, wide on the input side, with the select lines entering from below. A multiplexer is also called a data selector, and a 4-to-1 mux is often written 4×1 or 4:1.

2-to-1 multiplexer

Compact truth table

The compact table lists only the select line and says which input appears at the output. It is the table most data sheets print.

Full truth table

The full table treats the data inputs as inputs too, so a 2-to-1 mux, with three inputs in all, has eight rows. Row 0 has every input at 0:

Computed by the Tangibool engine

On rows 0 to 3, S is 0 and Y copies I0 (the middle input column). On rows 4 to 7, S is 1 and Y copies I1 (the last input column).

Expression and circuit

Read the compact table as two cases: the output is I0 when S is 0, and I1 when S is 1. So

Y = S′·I0 + S·I1

The circuit is one NOT gate for S′, two AND gates and one OR gate. The Karnaugh map solver arrives at the same two terms from the full table, and the truth table generator draws the four gates. The 2-to-1 multiplexer example works through the same circuit with the inputs named A and B.

In code, a 2-to-1 mux is the conditional operator: y = s ? i1 : i0 in C, Java and JavaScript, or y = i1 if s else i0 in Python.

From NAND gates only, a 2-to-1 mux takes four: one to invert S, and then the NAND-of-NANDs form of the two cases, NAND(NAND(I0, NAND(S, S)), NAND(I1, S)).

With an enable input

Many multiplexer chips add an enable input E that switches the whole mux off:

The expression gains one factor, Y = E·(S′·I0 + S·I1). On chips the enable is often active-low, drawn with a bubble and written E′ or Ē, so the mux works when that pin is 0. Enables let several multiplexers share one output line, with only one switched on at a time.

4-to-1 multiplexer

Compact truth table

Expression and circuit

Each row of the compact table becomes one term: the data input ANDed with the select pattern that picks it.

Y = S1′·S0′·I0 + S1′·S0·I1 + S1·S0′·I2 + S1·S0·I3

The circuit has two NOT gates for S1′ and S0′, four three-input AND gates, one per term, and one four-input OR gate. The two NOT gates and the select patterns of the AND gates together form a 2-to-4 decoder, so a mux can also be drawn as a decoder whose outputs gate the data inputs.

Full truth table: 64 rows

With its six inputs, two select lines and four data lines, the full truth table of a 4-to-1 mux has 2⁶ = 64 rows. The truth table generator builds all 64 from the expression above. The full table is rarely printed, because the compact one says the same thing: on every row, the output equals the data input that the select lines name. Reading a few rows of the full table is still a good way to see it. On the row S1 = 1, S0 = 0, I2 = 1 and every other input 0, the output is 1; change I2 to 0 and the output drops to 0, whatever I0, I1 and I3 do.

8-to-1 multiplexer

The expression has eight terms, one per row: Y = S2′S1′S0′·I0 + S2′S1′S0·I1 + … + S2S1S0·I7. Its full truth table would have 2¹¹ = 2,048 rows, which is why multiplexers are always described by the compact table.

Building bigger multiplexers from smaller ones

A 4-to-1 mux can be built from three 2-to-1 muxes. The first two share the select line S0: one chooses between I0 and I1, the other between I2 and I3. The third uses S1 to choose between their outputs:

Y = S1′·(S0′·I0 + S0·I1) + S1·(S0′·I2 + S0·I3)

Multiplying out the brackets gives the four-term expression above, and the equivalence checker confirms the cascade is the same circuit on all 64 rows. The same pattern scales: an 8-to-1 mux is two 4-to-1 muxes and a 2-to-1 on the top select line, and a 16-to-1 mux is five 4-to-1 muxes, four on the low select lines and one on the high ones.

Any Boolean function from one multiplexer

A multiplexer is a truth table in hardware: the select lines pick a row, and the data input on that row is the output. That gives two ways to build any function.

1. Put the truth table on the data inputs. For a function of three variables, connect them to the select lines of an 8-to-1 mux and tie each data input to 0 or 1, the function's value on that row. For the majority of three, which is 1 on rows 3, 5, 6 and 7, tie I3, I5, I6 and I7 to 1 and the rest to 0. The mux then computes Σm(A, B, C; 3, 5, 6, 7), the same as (A·B) + (A·C) + (B·C).

2. Use a smaller mux and the last variable. A function of three variables fits a 4-to-1 mux: A and B drive the select lines, and each data input is 0, 1, C or C′, whichever the function needs for that pair of A and B. For the majority:

The engine computes both columns, the mux wired this way and the majority function:

Computed by the Tangibool engine

They match on all eight rows, and the equivalence checker agrees. The same method gives the three-input parity function with the data inputs C, C′, C′, C: it equals A ⊕ B ⊕ C. Even a 2-to-1 mux computes XOR when S = A and the data inputs are B and B′: S′·B + S·B′ with S = A is A ⊕ B.

This is how FPGAs work: their basic cell, the lookup table, stores a function's truth table in memory bits and uses a multiplexer, driven by the function's inputs, to read out the right one.

Worked example: a 4-variable function on an 8-to-1 mux

A classic exercise: implement F(A, B, C, D) = Σm(1, 3, 4, 11, 12, 13, 14, 15) with one 8-to-1 multiplexer. Put A, B and C on the select lines. Each select pattern then covers two minterms, one with D = 0 and one with D = 1, and the data input for that pattern is whatever F does with D:

Written out, the mux with those inputs is A′B′C′·D + A′B′C·D + A′BC′·D′ + AB′C·D + ABC′ + ABC, and the equivalence checker confirms it is the function on all 16 rows. The method needs no simplification at all, which is why exam questions ask for it.

The 2-to-1 mux is a universal gate

With the constants 0 and 1 available, a 2-to-1 mux alone can build NOT, AND and OR, and so any circuit. Put A on the select line:

That is the same property that makes NAND and NOR universal, and it is why some chip families are built mostly from multiplexers.

Demultiplexer

A demultiplexer, or demux, does the reverse: it sends one data input D to one of several outputs, chosen by the select lines, and holds the other outputs at 0.

So Y0 = S′·D and Y1 = S·D. A 1-to-4 demux has two select lines and four outputs:

A demux and a mux driven by the same select lines pass a signal through and back: feeding the demux outputs Y0 and Y1 into a 2-to-1 mux gives S′·(S′·D) + S·(S·D), which is D again. That is the principle of time-division multiplexing, where several signals take turns on one wire. A demux with its data input tied to 1 is a decoder: exactly one output is 1, the one the select lines name.

Glitches and the consensus term

On paper, the 2-to-1 mux output does not change when S switches while I0 and I1 are both 1, because both terms give 1. In a real circuit, the S′·I0 term can turn off a moment before the S·I1 term turns on, and the output can dip to 0 for an instant: a static hazard, or glitch. The usual fix adds the redundant term I0·I1, which is 1 throughout. The consensus theorem says the extra term changes nothing logically, and the equivalence checker confirms that S′·I0 + S·I1 + I0·I1 is the same function. Tangibool's tools work with the logic, not with timing, so they show that the term is redundant but not the glitch it prevents.

Where multiplexers are used

• Processors. Muxes choose which register feeds the arithmetic unit, whether an operand comes from a register or from the instruction itself, and which result is written back.
• Shared buses and communication. Several sources take turns on one set of wires, and time-division multiplexing sends several signals over one line.
• FPGAs. Every lookup table is a multiplexer reading a stored truth table.
• Software. Every conditional expression, switch statement or array lookup by index is a multiplexer in code.

Summary

Common mistakes

1. Swapping the select polarity. With S = 0 the output is I0, not I1. Writing S·I0 + S′·I1 builds a mux whose inputs are crossed, and the equivalence checker finds the row S = F, I0 = F, I1 = T, where the two give different outputs.
2. Counting select lines wrongly. A mux with m data inputs needs log₂ m select lines: three for eight inputs, not eight.
3. Mixing up mux and demux. A mux has many inputs and one output; a demux has one input and many outputs.
4. Reading a mux as an OR of its inputs. A mux passes one input; the others are ignored, however they are set.
5. Leaving the enable inactive. Many mux chips have an enable input, often active-low, and hold the output at 0 when it is off.

Try it yourself

1. Write the mux as an expression, for example (NOT S AND I0) OR (S AND I1).
2. Open the truth table generator to see every row and the gate diagram, or the Karnaugh map solver to see how the terms group.
3. To check a function built on a mux, put the mux expression with its data inputs tied (use TRUE and FALSE for 1 and 0) and the function into the equivalence checker.

Frequently asked questions

What is a multiplexer?

A circuit that passes one of several data inputs to a single output, chosen by its select lines. It is also called a data selector.

What is the truth table of a 4-to-1 multiplexer?

S1 S0 = 00 gives I0, 01 gives I1, 10 gives I2 and 11 gives I3. Written with the data inputs as columns too, the table has 64 rows.

What is the Boolean expression of a 2-to-1 multiplexer?

Y = S′·I0 + S·I1: I0 when the select line is 0, I1 when it is 1.

How many select lines does an 8-to-1 multiplexer have?

Three, because 2³ = 8.

How do you make a 4-to-1 multiplexer from 2-to-1 multiplexers?

Use three: two choose within each pair of inputs using S0, and the third chooses between their outputs using S1.

How can a multiplexer implement a Boolean function?

Connect the function's variables to the select lines and tie each data input to the function's value on that row, or use one variable fewer on the select lines and feed 0, 1, the last variable or its complement into the data inputs.

What is the difference between a multiplexer and a demultiplexer?

A multiplexer selects one of many inputs for one output; a demultiplexer sends one input to one of many outputs.

What is a multiplexer used for?

Choosing data paths in processors, sharing one line between several signals, and building lookup tables in FPGAs.

Related pages

• Guides: encoders and decoders
• 2-to-1 multiplexer worked example and majority of three
• Combinational logic, minterms and the minterm expansion
• The consensus theorem and the consensus example
• Karnaugh maps, Lesson 11
• Practice: expressions to circuits, with answers

Written by Muaz Notiar. The Tangibool engine (semantics tangibool-semantics/1, engine 1.0.0) computed the 2 truth tables marked “Computed by the Tangibool engine”, and the 16 tool results the guide links to were re-run through the tools' own code in the build of 2026-11-07 and match what the text says. © 2026 Foreranger LTD.